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@epc-ake epc-ake commented Aug 7, 2025

Add the option to add PLL_D2 clock source for tx/rx clk of the i2s periphery of the esp32s3.

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Are those the only places where adding PLL_D2 can be used? If there are others, would you mind extending your PR to include them please?

@epc-ake epc-ake force-pushed the feature/add_PLL_D2_clk_to_i2s branch from a0b92ec to 14e5a9d Compare August 11, 2025 08:15
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epc-ake commented Aug 11, 2025

Are those the only places where adding PLL_D2 can be used? If there are others, would you mind extending your PR to include them please?

What do you mean with other places? Regarding I2S I think this covers it all.
The PLL_DC is also used in LCD_CAM and SAR_ADC:
I think both of them implement the PLL_D2 already.
SAR_ADC:
clk_tree_defs.h
adc_ll.h

LCD_CAM:
clk_tree_defs.h
cam_ll.h
lcd_ll.h

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Are those the only places where adding PLL_D2 can be used? If there are others, would you mind extending your PR to include them please?

What do you mean with other places? Regarding I2S I think this covers it all. The PLL_DC is also used in LCD_CAM and SAR_ADC: I think both of them implement the PLL_D2 already. SAR_ADC: clk_tree_defs.h adc_ll.h

LCD_CAM: clk_tree_defs.h cam_ll.h lcd_ll.h

Yes, I meant the other subsystems and drivers. It seems only I2S was missing this option.


/**
* @brief I2S clock source enum
*/
typedef enum {
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */
I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
I2S_CLK_SRC_PLL_D2 = SOC_MOD_CLK_PLL_D2, /*!< Select PLL_D2 as the source clock */
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Would you change this to the below and move it before 160MHz entry?

    I2S_CLK_SRC_PLL_240M = SOC_MOD_CLK_PLL_D2,                      /*!< Select PLL_D2 as the source clock.
                                                                         It is default to 240MHz while PLL is 480MHz,
                                                                         but it will be 160MHz if PLL is 320MHz */

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sylvioalves commented Aug 20, 2025

@epc-ake Would you also apply the same change into components/hal/esp32c6/include/hal/i2s_ll.h?
Then in components/soc/esp32c6/include/soc/clk_tree_defs.h:

/**
 * @brief Array initializer for all supported clock sources of I2S
 */
- #define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL}
+ #define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F240M, SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL}

/**
 * @brief I2S clock source enum
 */
typedef enum {
    I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M,                /*!< Select PLL_F160M as the default source clock  */
   +  I2S_CLK_SRC_PLL_240M = SOC_MOD_CLK_PLL_F240M,               /*!< Select PLL_F240M as the source clock */
    I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M,               /*!< Select PLL_F160M as the source clock */
    I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                        /*!< Select XTAL as the source clock */
    I2S_CLK_SRC_EXTERNAL = -1,                                  /*!< Select external clock as source clock */
} soc_periph_i2s_clk_src_t;

Let me know if you can do it. Otherwise we merge this and submit another. Thanks!

Add the option to add PLL_D2 clock source for tx/rx clk of the i2s periphery of the esp32s3.

Signed-off-by: Armin Kessler <[email protected]>
@epc-ake epc-ake force-pushed the feature/add_PLL_D2_clk_to_i2s branch from 14e5a9d to 4b3f2b1 Compare August 20, 2025 13:02
Add the option to add PLL_F240M clock source for tx/rx clk of the i2s periphery of the esp32c6.

Signed-off-by: Armin Kessler [email protected]
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epc-ake commented Aug 20, 2025

Let me know if you can do it. Otherwise we merge this and submit another. Thanks!

I added it as a second commit but I cant test it here.

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Let me know if you can do it. Otherwise we merge this and submit another. Thanks!

I added it as a second commit but I cant test it here.

Thanks!

@sylvioalves sylvioalves requested a review from marekmatej August 20, 2025 13:18
@sylvioalves sylvioalves merged commit 48a1274 into zephyrproject-rtos:main Aug 20, 2025
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5 participants